SystemVerilog · Sky130 · Open Source

Akmega

An ATmega-compatible 8-bit core taken from RTL to physical layout on Skywater 130nm. A bucket-list project to see how far one person and open-source tools can get.

View on GitHub →

01 Background

The question was simple enough

Could I take a complete microcontroller core from SystemVerilog all the way to a finished GDSII layout using only open-source tools? I'd tried something similar before with a RISC-V design, but that project failed at the placement stage—too much physical complexity for the automated flow.

So I scaled down. The ATmega architecture is one of the most widely-deployed 8-bit ISAs in the world, but as my friend Mike Matera pointed out, it's surprisingly poorly documented from an ISA perspective compared to modern standards. That gap made it an interesting target.

The ATmega toolchain visibility is often lacking, making it significantly tougher to bootstrap a custom core from scratch.
— Mike Matera, on the ATmega documentation gap

The entire core was developed through an interactive session with an LLM—an exploration of what's currently possible at the boundary of AI-assisted hardware engineering.

03 Pipeline

C firmware to silicon layout

The full flow compiles a C program (a Fibonacci sequence test), simulates the RTL against a behavioral golden model, and then pushes the design through synthesis, placement, routing, and signoff.

Compile

C → AVR binary
avr-gcc · atmega328p

→

Simulate

RTL execution
cocotb · Icarus Verilog

→

Verify

Golden model diff
Python · bit-perfect

→

Layout

RTL → GDSII
OpenLane · Sky130

04 Results

What came out of it

Simulation works. The core runs real C firmware compiled with avr-gcc. A Fibonacci program executes correctly and matches the golden model bit-for-bit at every cycle.
The layout completed. Unlike the earlier RISC-V attempt, this design made it through the entire OpenLane flow—synthesis, placement, CTS, routing, and signoff—to produce a valid GDSII on the Skywater 130nm process.
AXI4-Lite buses. Instead of the custom memory interface found in standard AVR cores, Akmega uses standard AXI4-Lite for both instruction fetch and data memory. This makes it straightforward to integrate into a larger SoC.
The whole thing is ~209 lines of SystemVerilog. Not a testament to cleverness—more a reflection of how much the ATmega ISA packs into a small surface area.

05 Usage

Running it yourself

Terminal

# Compile firmware, simulate RTL, verify against golden model
$ make verify

# Run the full ASIC flow (requires Docker + OpenLane)
$ make gds

Akmega

The question was simple enough

What's inside

C firmware to silicon layout

What came out of it

Running it yourself